The invention relates to a semiconductor device with a semiconductor body which is provided at a surface with a system of memory elements arranged in rows and columns and with a system of mutually adjacent, parallel selection lines which form row or column conductors for addressing the memory elements and which are each connected at an end to a selection transistor with which the connection between said conductor and peripheral electronics can be closed and opened.
Although the principle of the invention may be applied equally advantageously in a semiconductor device with a random-access memory, usually referred to in the literature by means of acronyms such as SRAM and DRAM, as will become clear below, the invention is particularly important for programmable non-volatile memories and (programmable) read-only memories (ROM) because of the high densities and/or voltages used therein. A widely used version of a programmable non-volatile memory is based on the use of a floating gate, wherein programming takes place by means of an electric charge applied to the floating gate, determining the threshold voltage of a MOST. The row conductors form, for example, the word lines by which a word can be selected in the memory matrix, whereas the column conductors act as bit lines. In another type of non-volatile memory for which the invention is particularly important, and which is described inter alia in U.S. Pat. No. 4,881,114, the memory elements comprise a thin dielectric layer between crossing silicon conductors of opposed conductivity types. In a specific embodiment, one of these conductors is formed by a surface zone in the semiconductor body, while the other one is formed by a poly layer deposited on the dielectric layer. Programming takes place here in that a voltage is applied between these conductors such that electric breakdown occurs across the dielectric layer, a pn junction arising between the conductors as a result. For the sake of simplicity, the selection lines will be referred to as word lines hereinafter also for this version. It should be noted, however, that the functions of word lines and bit lines may be interchanged in some versions.
For the purpose of addressing the memory elements, the peripheral electronics are provided inter alia with circuits with which an address is decoded into a signal for a selected line which is connected to the decoding circuit via a selection transistor. Usually the selection transistor is formed together with the remaining peripheral electronics in the semiconductor body. Given the continuous miniaturization owing to which the number of elements per unit surface area increases, the distances between the row conductors as well as the distances between the column conductors will become smaller and smaller. This miniaturization must correspond to the smallest dimensions in the peripheral electronics if a high packing density is to be realized in the matrix. The space necessary for controlling, for example, the word lines is found to be an important constraint with dimensions in the sub-micron range. In usual embodiments, the transistors are formed in the monocrystalline silicon and connected to row or column conductors provided on an oxide layer via contact windows in the oxide layer. It is not possible then to give the conductors a minimum pitch because of tolerances which are to be taken into account here. The fact that typical values of voltages applied to the word lines of an EPROM or a flash-EPROM for writing or erasing lie in a region between 12 and 16 V should also be taken into account with a further reduction of the dimensions. This means for silicon that, if electric breakdown is to be avoided, usual MOS transistors manufactured in the semiconductor body, mutually separated by field oxide and controlling adjacent word lines must be at least approximately 0.5 .mu.m removed from one another. Because of the necessary tolerances to be taken into account in designing, the minimum distance between adjacent word lines will be in excess of 0.5 .mu.m, so that it is useless to make the pitch in the memory matrix smaller than that. In summary, accordingly, the cell size may be substantially determined by the design rules in the periphery, so that in practice the cells are greater than they would have been if no attention were paid to the periphery in the design of the cell. This problem increases relatively in proportion as the minimum dimensions become smaller and/or the number of cells in the memory increases.